View AT49LV8011-90CC_6726534.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1 features ? single supply for read and write: 2.7v to 3.3v (bv), 3.0v to 3.3v (lv) access time ? 90 ns sector erase architecture fourteen 32k word (64k byte) sectors with individual write lockout two 16k word (32k byte) sectors with individual write lockout two 8k word (16k byte) sectors with individual write lockout four 4k word (8k byte) sectors with individual write lockout fast word program time ? 20 s fast sector erase time ? 200 ms dual plane organization, permitting concurrent read while program/erase memory plane a: four 4k word, two 8k word and two 16k word sectors memory plane b: fourteen 32k word sectors erase suspend capability ? supports reading/programming data from any sector by suspending erase of any different sector low-power operation ? 25 ma active ? 10 a standby data polling, toggle bit, ready/busy for end of program detection optional vpp pin for fast programming reset input for device initialization sector program unlock command tsop and cbga package options top or bottom boot block configuration available description the at49bv/lv8011(t) is a 2.7- to 3.3-volt 8-megabit flash memory organized as 524,288 words of 16 bits each or 1,048,576 bytes of 8 bits each. the x16 data appears on i/o0 - i/o15; the x8 data appears on i/o0 - i/o7. the memory is divided into 22 sectors for erase operations. the device is offered in 48-pin tsop and 48-ball cbga packages. the device has ce , and oe control signals to avoid any bus rev. 1265e ? 01/00 8-megabit (512k x 16/1m x 8) 3-volt only flash memory at49bv8011 at49bv8011t at49lv8011 at49lv8011t pin configurations pin name function a0 - a18 addresses ce chip enable oe output enable we write enable reset reset rdy/busy ready/busy output vpp optional power supply for faster program/erase operations i/o0 - i/o14 data inputs/outputs i/o15 (a-1) i/o15 (data input/output, word mode) a-1 (lsb address input, byte mode) byte selects byte or word mode nc no connect vccq output power supply (continued)
at49bv/lv8011(t) 2 contention. this device can be read or reprogrammed using a single 2.7v power supply, making it ideally suited for in-system programming. the device powers on in the read mode. command sequences are used to place the device in other operation modes such as program and erase. the device has the capability to protect the data in any sector. once the data protection for a given sector is enabled, the data in that sector cannot be changed using input levels between ground and v cc . the device is segmented into two memory planes. reads from memory plane b may be performed even while pro- gram or erase functions are being executed in memory plane a and vice versa. this operation allows improved system performance by not requiring the system to wait for a program or erase operation to complete before a read is performed. to further increase the flexibility of the device, it contains an erase suspend feature. this feature will put the erase on hold for any amount of time and let the user read data from or program data to any of the remaining sectors within the same memory plane. there is no reason to suspend the erase operation if the data to be read is in the other memory plane. the end of a program or an erase cycle is detected by the ready/busy pin, data polling, or by the toggle bit. a vpp pin is provided to improve program/erase times. this pin can be tied to v cc . to take advantage of faster programming and erasing, the pin should supply 4.5 to 5.5 volts during program and erase operations. a 6-byte command (bypass unlock) sequence to remove the requirement of entering the 3-byte program sequence is offered to further improve programming time. after enter- ing the 6-byte code, only single pulses on the write control lines are required for writing into the device. this mode (single-pulse byte/word program) is exited by powering down the device, or by pulsing the reset pin low for a minimum of 50 ns and then bringing it back to v cc . erase and erase suspend/resume commands will not work while in this mode; if entered they will result in data being pro- grammed into the device. it is not recommended that the 6-byte code reside in the software of the final product but only exist in external programming code. the byte pin controls whether the device data i/o pins operate in the byte or word configuration. if the byte pin is set at logic ? 1 ? , the device is in word configuration, i/o0 - i/o15 are active and controlled by ce and oe . if the byte pin is set at logic ? 0 ? , the device is in byte con- figuration, and only data i/o pins i/o0 - i/o7 are active and controlled by ce and oe . the data i/o pins i/o8 - i/o14 are tri-stated, and the i/o15 pin is used as an input for the lsb (a-1) address function. cbga top view rdy/busy nc a18 nc i/o2 i/o10 i/o11 i/o3 a3 a4 a2 a1 a0 ce oe vss a7 a17 a6 a5 i/o0 i/o8 i/o9 i/o1 we reset vpp nc i/o5 i/o12 vcc i/o4 a9 a8 a10 a11 i/o7 i/o14 i/o13 i/o6 a13 a12 a14 a15 a16 byte i/o15 vss a b c d e f g h 1 23456 /a-1 tsop top view type 1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 a15 a14 a13 a12 a11 a10 a9 a8 nc nc we reset vpp nc rdy/busy a18 a17 a7 a6 a5 a4 a3 a2 a1 a16 byte gnd i/o15/a-1 i/o7 i/o14 i/o6 i/o13 i/o5 i/o12 i/o4 vcc i/o11 i/o3 i/o10 i/o2 i/o9 i/o1 i/o8 i/o0 oe gnd ce a0
at49bv/lv8011(t) 3 block diagram device operation read: the at49bv/lv8011(t) is accessed like an eprom. when ce and oe are low and we is high, the data stored at the memory location determined by the address pins are asserted on the outputs. the outputs are put in the high impedance state whenever ce or oe is high. this dual line control gives designers flexibility in pre- venting bus contention. command sequences: when the device is first pow- ered on it will be reset to the read or standby mode, depending upon the state of the control line inputs. in order to perform other device functions, a series of command sequences are entered into the device. the command sequences are shown in the command definitions table (i/o8 - i/o15 are don ? t care inputs for the command codes). the command sequences are written by applying a low pulse on the we or ce input with ce or we low (respec- tively) and oe high. the address is latched on the falling edge of ce or we , whichever occurs last. the data is latched by the first rising edge of ce or we . standard microprocessor write timings are used. the address locations used in the command sequences are not affected by entering the command sequences. reset: a reset input pin is provided to ease some sys- tem applications. when reset is at a logic high level, the device is in its standard operating mode. a low level on the reset input halts the present device operation and puts the outputs of the device in a high impedance state. when a high level is reasserted on the reset pin, the device returns to the read or standby mode, depending upon the state of the control inputs. by applying a 12v 0.5v input signal to the reset pin, any sector can be reprogrammed even if the sector lockout feature has been enabled (see ? sector programming lockout override ? section). erasure: before a byte/word can be reprogrammed, it must be erased. the erased state of memory bits is a logi- cal ? 1 ? . the entire device can be erased by using the chip erase command or individual sectors can be erased by using the sector erase commands. identifier register status register data comparator output multiplexer output buffer input buffer command register data register y-gating write state machine program/erase voltage switch ce we oe reset byte rdy/busy vpp vcc gnd y-decoder x-decoder input buffer address latch i/o0 - i/o15/a-1 a0 - a18 plane b sectors plane a sectors
at49bv/lv8011(t) 4 chip erase: the entire device can be erased at one time by using the 6-byte chip erase software code. after the chip erase has been initiated, the device will internally time the erase operation so that no external clocks are required. the maximum time to erase the chip is t ec . if the sector lockout has been enabled, the chip erase will not erase the data in the sector that has been locked; it will erase only the unprotected sectors. after the chip erase, the device will return to the read or standby mode. sector erase: as an alternative to a full chip erase, the device is organized into 22 sectors that can be individually erased. the sector erase command is a six bus cycle operation. the sector address is latched on the falling we edge of the sixth cycle while the 30h data input command is latched on the rising edge of we . the sector erase starts after the rising edge of we of the sixth cycle. the erase operation is internally controlled; it will automatically time to completion. the maximum time to erase a section is t sec . when the sector programming lockout feature is not enabled, the sector will erase (from the same sector erase command). once a sector has been protected, data in the protected sectors cannot be changed unless the reset pin is taken to 12v 0.5v. an attempt to erase a sector that has been protected will result in the operation terminat- ing in 2 s. byte/word programming: once a memory block is erased, it is programmed (to a logical ? 0 ? ) on a byte-by-byte or on a word-by-word basis. programming is accomplished via the internal device command register and is a four bus cycle operation. the device will automatically generate the required internal program pulses. any commands written to the chip during the embedded programming cycle will be ignored. if a hardware reset hap- pens during programming, the data at the location being programmed will be corrupted. please note that a data ? 0 ? cannot be programmed back to a ? 1 ? ; only erase operations can convert ? 0 ? s to ? 1 ? s. programming is completed after the specified t bp cycle time. the data polling feature or the toggle bit feature may be used to indicate the end of a program cycle. sector programming lockout: each sector has a programming lockout feature. this feature prevents pro- gramming of data in the designated sectors once the feature has been enabled. these sectors can contain secure code that is used to bring up the system. enabling the lockout feature will allow the boot code to stay in the device while data in the rest of the device is updated. this feature does not have to be activated; any sector ? s usage as a write-protected region is optional to the user. once the feature is enabled, the data in the protected sec- tors can no longer be erased or programmed when input levels of 5.5v or less are used. data in the remaining sectors can still be changed through the regular program- ming method. to activate the lockout feature, a series of six program commands to specific addresses with specific data must be performed. please refer to the command definitions table. sector lockout detection: a software method is available to determine if programming of a sector is locked out. when the device is in the software product identifica- tion mode (see ? software product identification entry/exit ? sections), a read from address location 00002h within a sector will show if programming the sector is locked out. if the data on i/o0 is low, the sector can be programmed; if the data on i/o0 is high, the program lockout feature has been enabled and the sector cannot be programmed. the software product identification exit code should be used to return to standard operation. sector programming lockout override: the user can override the sector programming lockout by taking the reset pin to 12v 0.5v. by doing this, protected data can be altered through a chip erase, sector erase or byte/word programming. when the reset pin is brought back to ttl levels, the sector programming lockout feature is again active. erase suspend/erase resume: the erase sus- pend command allows the system to interrupt a sector erase operation and then program or read data from a dif- ferent sector within the same plane. since this device has a dual plane architecture, there is no need to use the erase suspend feature while erasing a sector when you want to read data from a sector in the other plane. after the erase suspend command is given, the device requires a maxi- mum time of 15 s to suspend the erase operation. after the erase operation has been suspended, the plane that contains the suspended sector enters the erase-suspend- read mode. the system can then read data or program data to any other sector within the device. an address is not required during the erase suspend command. during a sector erase suspend, another sector cannot be erased. to resume the sector erase operation, the system must write the erase resume command. the erase resume com- mand is a one bus cycle command that does require the plane address, which is determined by a18 - a16. the device also supports an erase suspend during a complete chip erase. while the chip erase is suspended, the user can read from any sector within the memory that is pro- tected. the command sequence for a chip erase suspend and a sector erase suspend are the same. product identification: the product identification mode identifies the device and manufacturer as atmel. it may be accessed by hardware or software operation. the hardware operation mode can be used by an external pro- grammer to identify the correct programming algorithm for the atmel product.
at49bv/lv8011(t) 5 for details, see ? operating modes ? (for hardware opera- tion) or ? software product identification ? . the manufacturer and device code is the same for both modes. data polling: the at49bv/lv8011(t) features data polling to indicate the end of a program cycle. during a pro- gram cycle an attempted read of the last byte/word loaded will result in the complement of the loaded data on i/o7. once the program cycle has been completed, true data is valid on all outputs and the next cycle may begin. during a chip or sector erase operation, an attempt to read the device will give a ? 0 ? on i/o7. once the program or erase cycle has completed, true data will be read from the device. data polling may begin at any time during the program cycle. please see ? status bit table ? for more details. toggle bit: in addition to data polling, the at49bv/lv8011(t) provides another method for determin- ing the end of a program or erase cycle. during a program or erase operation, successive attempts to read data from the same memory plane will result in i/o6 toggling between ? 1 ? and ? 0 ? . once the program cycle has completed, i/o6 will stop toggling and valid data will be read. examining the toggle bit may begin at any time during a program cycle. an additional toggle bit is available on i/o2, which can be used in conjunction with the toggle bit that is available on i/o6. while a sector is erase suspended, a read or a program operation from the suspended sector will result in the i/o2 bit toggling. please see ? status bit table ? for more details. rdy/busy : an open drain ready/busy output pin pro- vides another method of detecting the end of a program or erase operation. rdy/busy is actively pulled low during the internal program and erase cycles and is released at the completion of the cycle. the open drain connection allows for or-tying of several devices to the same rdy/busy line. hardware data protection: hardware features protect against inadvertent programs to the at49bv/lv8011(t) in the following ways: (a) v cc sense: if v cc is below 1.8v (typical), the program function is inhib- ited. (b) v cc power on delay: once v cc has reached the v cc sense level, the device will automatically time out 10 ms (typical) before programming. (c) program inhibit: holding any one of oe low, ce high or we high inhibits program cycles. (d) noise filter: pulses of less than 15 ns (typical) on the we or ce inputs will not initiate a program cycle. input levels: while operating with a 2.7v to 3.3v power supply, the address inputs and control inputs (oe , ce , and we ) may be driven from 0 to 5.5v without adversely affecting the operation of the device. the i/o lines can only be driven from 0 to v cc + 0.6v.
at49bv/lv8011(t) 6 notes: 1. the data format in each bus cycle is as follows: i/o15 - i/o8 (don ? t care); i/o7 - i/o0 (hex). the address format in each bus cycle is as follows: a15 - a0 (hex). address a18 through a14 are don ? t care in the word mode. address a18 through a14 and a-1 are don ? t care in the byte mode. 2. either one of the product id exit commands can be used. 3. sa = sector address. any byte/word address within a sector can be used to designate the sector address (see next two pages for details). 4. when the sector programming lockout feature is not enabled, the sector will erase (from the same sector erase command). once the sector has been protected, data in the protected sectors cannot be changed unless the reset pin is taken to 12v 0.5v. 5. pa is the plane address (a18 - a16). command definition in (hex) (1) command sequence bus cycles 1st bus cycle 2nd bus cycle 3rd bus cycle 4th bus cycle 5th bus cycle 6th bus cycle addr data addr data addr data addr data addr data addr data read 1 addr d out chip erase 6 5555 aa 2aaa 55 5555 80 5555 aa 2aaa 55 5555 10 sector erase 6 5555 aa 2aaa 55 5555 80 5555 aa 2aaa 55 sa (3)(4) 30 byte/word program 4 5555 aa 2aaa 55 5555 a0 addr d in bypass unlock 6 5555 aa 2aaa 55 5555 80 5555 aa 2aaa 55 5555 a0 single-pulse byte/word program 1 addr d in sector lockout 6 5555 aa 2aaa 55 5555 80 5555 aa 2aaa 55 sa (3)(4) 40 erase suspend 1 xxxx b0 erase resume 1 pa (5) 30 product id entry 3 5555 aa 2aaa 55 5555 90 product id exit (2) 3 5555 aa 2aaa 55 5555 f0 product id exit (2) 1 xxxx f0 absolute maximum ratings* temperature under bias ................................ -55 c to +125 c *notice: stresses beyond those listed under ? absolute maximum ratings ? may cause permanent dam- age to the device. this is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. storage temperature ..................................... -65 c to +150 c all input voltages (including nc pins) with respect to ground ...................................-0.6v to +6.25v all output voltages with respect to ground .............................-0.6v to v cc + 0.6v voltage on oe with respect to ground ...................................-0.6v to +13.5v
at49bv/lv8011(t) 7 at49bv/lv8011 ? sector address table plane sector size (bytes/words) x8 address range (a18 - a-1) x16 address range (a18 - a0) a sa0 16k/8k 000000 - 003fff 00000 - 01fff a sa1 32k/16k 004000 - 00bfff 02000 - 05fff a sa2 8k/4k 00c000 - 00dfff 06000 - 06fff a sa3 8k/4k 00e000 - 00ffff 07000 - 07fff a sa4 8k/4k 010000 - 011fff 08000 - 08fff a sa5 8k/4k 012000 - 013fff 09000 - 09fff a sa6 32k/16k 014000 - 018fff 0a000 - 0dfff a sa7 16k/8k 01c000 - 01ffff 0e000 - 0ffff b sa8 64k/32k 020000 - 02ffff 10000 - 17fff b sa9 64k/32k 030000 - 03ffff 18000 - 1ffff b sa10 64k/32k 040000 - 04ffff 20000 - 27fff b sa11 64k/32k 050000 - 05ffff 28000 - 2ffff b sa12 64k/32k 060000 - 06ffff 30000 - 37fff b sa13 64k/32k 070000 - 07ffff 38000 - 3ffff b sa14 64k/32k 080000 - 08ffff 40000 - 47fff b sa15 64k/32k 090000 - 09ffff 48000 - 4ffff b sa16 64k/32k 0a0000 - 0affff 50000 - 57fff b sa17 64k/32k 0b0000 - 0bffff 58000 - 5ffff b sa18 64k/32k 0c0000 - 0cffff 60000 - 67fff b sa19 64k/32k 0d0000 - 0dffff 68000 - 6ffff b sa20 64k/32k 0e0000 - 0effff 70000 - 77fff b sa21 64k/32k 0f0000 - 0fffff 78000 - 7ffff
at49bv/lv8011(t) 8 at49bv/lv8011t ? sector address table plane sector size (bytes/words) x8 address range (a18 - a-1) x16 address range (a18 - a0) b sa0 64k/32k 000000 - 00ffff 00000 - 07fff b sa1 64k/32k 010000 - 01ffff 08000 - 0ffff b sa2 64k/32k 020000 - 02ffff 10000 - 17fff b sa3 64k/32k 030000 - 03ffff 18000 - 1ffff b sa4 64k/32k 040000 - 04ffff 20000 - 27fff b sa5 64k/32k 050000 - 05ffff 28000 - 2ffff b sa6 64k/32k 060000 - 06ffff 30000 - 37fff b sa7 64k/32k 070000 - 07ffff 38000 - 3ffff b sa8 64k/32k 080000 - 08ffff 40000 - 47fff b sa9 64k/32k 090000 - 09ffff 48000 - 4ffff b sa10 64k/32k 0a0000 - 0affff 50000 - 57fff b sa11 64k/32k 0b0000 - 0bffff 58000 - 5ffff b sa12 64k/32k 0c0000 - 0cffff 60000 - 67fff b sa13 64k/32k 0d0000 - 0dffff 68000 - 6ffff a sa14 16k/8k 0e0000 - 0e3fff 70000 - 71fff a sa15 32k/16k 0e4000 - 0ebfff 72000 - 75fff a sa16 8k/4k 0ec000 - 0edfff 76000 - 76fff a sa17 8k/4k 0ee000 - 0effff 77000 - 77fff a sa18 8k/4k 0f0000 - 0f1fff 78000 - 78fff a sa19 8k/4k 0f2000 - 0f3fff 79000 - 79fff a sa20 32k/16k 0f4000 - 0fbfff 7a000 - 7dfff a sa21 16k/8k 0fc000 - 0fffff 7e000 - 7ffff
at49bv/lv8011(t) 9 notes: 1. x can be v il or v ih . 2. refer to ac programming waveforms. 3. v h = 12.0v 0.5v. 4. manufacturer code: 1fh (x8); 001fh (x16), device code: 00cb-at49bv8011; 004a-at49bv8011t. 5. see details under ? software product identification entry/exit ? . 6. for faster program/erase operations, v pp = 5v 10%. note: 1. in the erase mode, i cc is 50 ma. dc and ac operating range at49lv8011(t)-90 at49bv8011(t)-12 operating temperature (case) com. 0 c - 70 c0 c - 70 c ind. -40 c - 85 c-40 c - 85 c v cc power supply 3.0v to 3.3v 2.7v to 3.3v operating modes mode ce oe we reset v pp (6) ai i/o read v il v il v ih v ih xaid out program/erase (2) v il v ih v il v ih v cc ai d in standby/program inhibit v ih x (1) xv ih x x high-z program inhibit x x v ih v ih x program inhibit x v il xv ih x output disable x v ih xv ih x high-z reset xxx v il x x high-z product identification hardware v il v il v ih v ih a1 - a18 = v il , a9 = v h (3) , a0 = v il manufacturer code (4) a1 - a18 = v il , a9 = v h (3) , a0 = v ih device code (4) software (5) v ih a0 = v il , a1 - a18 = v il manufacturer code (4) a0 = v ih , a1 - a18 = v il device code (4) dc characteristics symbol parameter condition min max units i li input load current v in = 0v to v cc 10 a i lo output leakage current v i/o = 0v to v cc 10 a i sb1 v cc standby current cmos ce = v cc - 0.3v to v cc 10 a i sb2 v cc standby current ttl ce = 2.0v to v cc 1ma i cc (1) v cc active current f = 5 mhz; i out = 0 ma 30 ma i ccrw v cc read while write current f = 5 mhz; i out = 0 ma 50 ma v il input low voltage 0.6 v v ih input high voltage 2.0 v v ol output low voltage i ol = 2.1 ma 0.45 v v oh output high voltage i oh = -400 a 2.4 v
at49bv/lv8011(t) 10 ac read waveforms (1)(2)(3)(4) notes: 1. ce may be delayed up to t acc - t ce after the address transition without impact on t acc . 2. oe may be delayed up to t ce - t oe after the falling edge of ce without impact on t ce or by t acc - t oe after an address change without impact on t acc . 3. t df is specified from oe or ce whichever occurs first (cl = 5 pf). 4. this parameter is characterized and is not 100% tested. input test waveforms and measurement level t r , t f < 5 ns output test load note: 1. this parameter is characterized and is not 100% tested. ac read characteristics symbol parameter at49lv8011(t)-90 at49bv8011(t)-12 units min max min max t acc address to output delay 90 120 ns t ce (1) ce to output delay 90 120 ns t oe (2) oe to output delay 0 40 0 50 ns t df (3)(4) ce or oe to output float 0 25 0 30 ns t oh output hold from oe , ce or address, whichever occurred first 0 0 ns t ro reset to output delay 800 800 ns output valid output high z reset oe toe tce address valid tdf toh tacc tro ce address pin capacitance f = 1 mhz, t = 25 c (1) symbol typ max units conditions c in 46pfv in = 0v c out 812pfv out = 0v
at49bv/lv8011(t) 11 ac byte/word load waveforms we controlled ce controlled ac byte/word load characteristics symbol parameter min max units t as , t oes address, oe setup time 10 ns t ah address hold time 100 ns t cs chip select setup time 0 ns t ch chip select hold time 0 ns t wp write pulse width (we or ce ) 100 ns t ds data setup time 100 ns t dh , t oeh data, oe hold time 10 ns t wph write pulse width high 50 ns
at49bv/lv8011(t) 12 program cycle waveforms sector or chip erase cycle waveforms notes: 1. oe must be high only when we and ce are both low. 2. for chip erase, the address should be 5555. for sector erase, the address depends on what sector is to be erased. (see note 3 under command definitions.) 3. for chip erase, the data should be 10h, and for sector erase, the data should be 30h. 4. the t wph time between the 5th and 6th bus cycle should be a minimum of 150 ns. program cycle characteristics symbol parameter min typ max units t bp byte/word programming time 20 50 s t as address setup time 0 ns t ah address hold time 100 ns t ds data setup time 100 ns t dh data hold time 10 ns t wp write pulse width 100 ns t wph write pulse width high 50 ns t ec chip erase cycle time 10 seconds t sec sector erase cycle time 200 ms oe program cycle input data address a0 55 5555 5555 aa 2aaa t bp t wph t wp ce we a0 -a18 data t as t ah t dh t ds 5555 aa oe (1) aa 80 note 3 55 55 5555 5555 note 2 aa word 0 word 1 word 2 word 3 word 4 word 5 2aaa 2aaa t wph t wp ce we a0-a18 data t as t ah t ec t dh t ds 5555 (4) (4)
at49bv/lv8011(t) 13 notes: 1. these parameters are characterized and not 100% tested. 2. see t oe spec in ? ac read characteristics ? . data polling waveforms notes: 1. these parameters are characterized and not 100% tested. 2. see t oe spec in ? ac read characteristics ? . toggle bit waveforms (1)(2)(3) notes: 1. toggling either oe or ce or both oe and ce will operate toggle bit. the t oehp specification must be met by the toggling input(s). 2. beginning and ending state of i/o6 will vary. 3. any address location may be used but the address should not vary. data polling characteristics (1) symbol parameter min typ max units t dh data hold time 10 ns t oeh oe hold time 10 ns t oe oe to output delay (2) ns t wr write recovery time 0 ns a0-a18 toggle bit characteristics (1) symbol parameter min typ max units t dh data hold time 10 ns t oeh oe hold time 10 ns t oe oe to output delay (2) ns t oehp oe high pulse 150 ns t wr write recovery time 0 ns
at49bv/lv8011(t) 14 software product identification entry (1) software product identification exit (1)(7) notes: 1. data format: i/o15 - i/o8 (don ? t care); i/o7 - i/o0 (hex) address format: a15 - a0 (hex), a-1, and a15 - a18 (don ? t care). 2. a1 - a18 = v il . manufacture code is read for a0 = v il ; device code is read for a0 = v ih . 3. the device does not remain in identification mode if pow- ered down. 4. the device returns to standard operation mode. 5. manufacturer code: 1fh(x8); 001fh(x16) 6. device code: 00cb-at49bv8011; 004a-at49bv8011t. 7. either one of the product id exit commands can be used. sector lockout enable algorithm (1) notes: 1. data format: i/o15 - i/o8 (don ? t care); i/o7 - i/o0 (hex) address format: a15 - a0 (hex), a-1, and a15 - a18 (don ? t care). 2. sector lockout feature enabled. load data aa to address 5555 load data 55 to address 2aaa load data 90 to address 5555 enter product identification mode (2)(3)(5) load data aa to address 5555 load data 55 to address 2aaa load data f0 to address 5555 exit product identification mode (4) or load data f0 to any address exit product identification mode (4) load data aa to address 5555 load data 55 to address 2aaa load data 80 to address 5555 load data aa to address 5555 load data 55 to address 2aaa load data 40 to address 5555 pause 200 s (2)
at49bv/lv8011(t) 15 status bit table status bit i/o7 i/o6 i/o2 read address in plane a plane b plane a plane b plane a plane b while programming in plane a i/o7 data toggle data 1 data programming in plane b data i/o7 data toggle data 1 erasing in plane a 0 data toggle data toggle data erasing in plane b data 0 data toggle data toggle erase suspended & read erasing sector 1 1 1 1 toggle toggle erase suspended & read non-erasing sector data data data data data data erase suspended & program erasing sector 1 1 1 1 toggle toggle erase suspended & program non-erasing sector in plane a i/o7 data toggle data toggle data erase suspended & program non-erasing sector in plane b data i/o7 data toggle data toggle
at49bv/lv8011(t) 16 at49bv/lv8011(t) ordering information t acc (ns) i cc (ma) ordering code package operation range active standby 90 25 0.01 AT49LV8011-90CC at49lv8011-90tc 48c3 48t commercial (0 to 70 c) 25 0.01 at49lv8011-90ci at49lv8011-90ti 48c3 48t industrial (-40 to 85 c) 120 25 0.01 at49bv8011-12cc at49bv8011-12tc 48c3 48t commercial (0 to 70 c) 25 0.01 at49bv8011-12ci at49bv8011-12ti 48c3 48t industrial (-40 to 85 c) 90 25 0.01 at49lv8011t-90cc at49lv8011t-90tc 48c3 48t commercial (0 to 70 c) 25 0.01 at49lv8011t-90ci at49lv8011t-90ti 48c3 48t industrial (-40 to 85 c) 120 25 0.01 at49bv8011t-12cc at49bv8011t-12tc 48c3 48t commercial (0 to 70 c) 25 0.01 at49bv8011t-12ci at49bv8011t-12ti 48c3 48t industrial (-40 to 85 c) package type 48c3 48-ball, plastic chip-size ball grid array package (cbga) 48t 48-lead, thin small outline package (tsop)
at49bv/lv8011(t) 17 packaging information *controlling dimension: millimeters a b c d e f g h 65 4 3 21 4.0 (0.157) 0.46 (0.018) dia ball typ 5.6 (0.220) 1.20 (0.047) 1.00 (0.039) 0.30 (0.012) 7.15 (0.281) 6.85 (0.270) 7.15 (0.281) 6.85 (0.270) 0.80 (0.031) bsc non-accumulative *controlling dimension: millimeters 48c3, 48-ball, plastic chip-size ball grid array package (cbga) dimensions in millimeters and (inches)* 48t, 48-lead, plastic thin small outline package (tsop) dimensions in millimeters and (inches)* jedec outline mo-142 dd
? atmel corporation 2000. atmel corporation makes no warranty for the use of its products, other than those expressly contained in the company ? s standard war- ranty which is detailed in atmel ? s terms and conditions located on the company ? s web site. the company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any tim e without notice, and does not make any commitment to update the information contained herein. no licenses to patents or other intellectu al prop- erty of atmel are granted by the company in connection with the sale of atmel products, expressly or by implication. atmel ? s products are not authorized for use as critical components in life support devices or systems. atmel headquarters atmel operations corporate headquarters 2325 orchard parkway san jose, ca 95131 tel (408) 441-0311 fax (408) 487-2600 europe atmel u.k., ltd. coliseum business centre riverside way camberley, surrey gu15 3yl england tel (44) 1276-686-677 fax (44) 1276-686-697 asia atmel asia, ltd. room 1219 chinachem golden plaza 77 mody road tsimhatsui east kowloon hong kong tel (852) 2721-9778 fax (852) 2722-1369 japan atmel japan k.k. 9f, tonetsu shinkawa bldg. 1-24-8 shinkawa chuo-ku, tokyo 104-0033 japan tel (81) 3-3523-3551 fax (81) 3-3523-7581 atmel colorado springs 1150 e. cheyenne mtn. blvd. colorado springs, co 80906 tel (719) 576-3300 fax (719) 540-1759 atmel rousset zone industrielle 13106 rousset cedex france tel (33) 4-4253-6000 fax (33) 4-4253-6001 fax-on-demand north america: 1-(800) 292-8635 international: 1-(408) 441-0732 e-mail literature@atmel.com web site http://www.atmel.com bbs 1-(408) 436-4309 printed on recycled paper. 1265e ? 01/00/xm marks bearing ? and/or ? are registered trademarks and trademarks of atmel corporation. terms and product names in this document may be trademarks of others.

▲Up To Search▲

Price & Availability of AT49LV8011-90CC

	To Download AT49LV8011-90CC Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .